This invention relates to a method, compositions, and additives for electrolytic copper metallization of silicon wafers in the manufacture of semiconductor integrated circuit (IC) devices.
The demand for manufacturing semiconductor IC devices such as computer chips with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultra-large-scale integration (ULSI) and very-large-scale integration (VLSI) structures. The trend to smaller chip sizes and increased circuit density requires the miniaturization of interconnect features which severely penalizes the overall performance of the structure because of increasing interconnect resistance and reliability concerns such as electromigration.
Traditionally, such structures had used aluminum and aluminum alloys as the metallization on silicon wafers with silicon dioxide being the dielectric material. In general, openings are formed in the dielectric layer in the shape of vias and trenches after metallization to form the interconnects. Increased miniaturization is reducing the openings to submicron sizes (e.g., 0.5 micron and lower).
To achieve further miniaturization of the device, copper has been introduced instead of aluminum as the metal to form the connection lines and interconnects in the chip. Copper metallization is carried out after forming the interconnects. Copper has a lower resistivity than aluminum and the thickness of a copper line for the same resistance can be thinner than that of an aluminum line. Copper-based interconnects therefore represent the future trend in the fabrication of such devices.
Copper can be deposited on substrates by plating (such as electroless and electrolytic), sputtering, plasma vapor deposition (PVD), and chemical vapor deposition (CVD). It is generally recognized electrochemical deposition is the best method to apply copper to the device since it can provide high deposition rates and low tool costs. However, plating methods must meet the stringent requirements of the semiconductor industry. For example, the copper deposits must be uniform and capable of flawlessly filling the extremely small trenches and vias of the device. The plating process must also be capable of being controlled so that process variation is minimized. The deposition of copper from acid copper baths is recognized in the electronics industry as the leading candidate to copper plate integrated circuit devices.
Copper electroplating, in general, involves deposition of a copper layer onto a surface by means of electrolysis using a consumable copper electrode or an insoluble anode.
Regardless of the method used to deposit copper on the substrate surface impurities may be co-deposited with the copper and other morphological defects introduced. In IC fabrication it is important that impurity particles not be present in the electrolyte but such impurities may result from anode sludges formed during the plating operation.
Other micro-defects which adversely affect conductivity in deposited copper result from internal voiding and voiding attributable to detachment of the deposited copper from the walls of features including vias and trenches.